• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: An option control circuit is provided to reduce a hardware size and simplify design by integrating a program ROM and an option ROM CONSTITUTION: An option control circuit comprises an option address generator, a multiplexer, a program memory and a latch. The option address generator(202) drives by an option lead signal(OR) and outputs an option address. An external address, an option address and an option lead signal (OR) as a choice signal are input to the multiplexer(204) through the address bus. Then, an address is inputted to the program memory(206) through the multiplexer (204) and a system control program containing option data is stored. The data output from the program memory(206) and an option lead signal(OR) as a clock signal are inputted to the latch(208) through the data bus.
    公开号:KR20000021213A
    申请号:KR1019980040211
    申请日:1998-09-28
    公开日:2000-04-25
    发明作者:김호현
    申请人:김영환；현대반도체 주식회사；
    IPC主号:
    专利说明:

    Optional control circuit
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an option control circuit, and more particularly, to an option control circuit for changing a system setting by executing a predetermined option program by an option read signal.
    It is common to set various kinds of options in a semiconductor circuit. Such an option means whether to use an external crystal oscillator or an internal RC oscillator circuit as the oscillation means, or hardware means such as current / voltage characteristics and pull-up / pull-down options.
    1 is a view showing a conventional option control circuit.
    The option ROM 102 stores option data. When the option read signal OR is activated, the option data stored in the option ROM 102 is output. The option data output from the option ROM 102 is output through the latch 104. The latch 104 uses the above-described option read signal OR as a clock signal.
    Also shown in FIG. 1 is a program ROM 106, which stores a program for generating various control signals necessary for the operation of the system. However, this program ROM 106 is a separate memory from the option ROM 102.
    The user codes the desired option data into the option ROM 102. The option lead signal OR is generated through a reset signal or the like. The option read signal OR is activated before the program ROM 106 operates so that the option data of the option ROM 102 is stored in the latch 104. The output of the option data DOP of the latch 104 is also caused by the activation of the option read signal OR.
    In the conventional option control circuit, a separate option ROM for storing option data is provided in addition to the program ROM basically built into the system. To configure this option ROM, the memory cell array, sense amplifier and other control circuits must be designed.
    In addition, I / O pins are increased because a separate control mode is required to control the option ROM.
    Therefore, an object of the present invention is to enable the integrated operation of the program ROM and the option ROM.
    The present invention for this purpose comprises an option address generator, a multiplexer, a program memory, and a latch.
    The option address generator 202 operates by the option read signal OR to output the option address.
    The multiplexer 204 is input with an external address and an option address transmitted via an address bus, and an option read signal OR is input as a selection signal.
    A predetermined address is input to the program memory 206 through the multiplexer 204, and a predetermined system control program including option data is stored.
    Data output from the program memory 206 is input to the latch 208 through the data bus, and the option read signal OR is input as a clock signal.
    1 is a view showing a conventional option control circuit.
    2 shows an option control circuit according to the invention;
    Explanation of symbols on the main parts of the drawings
    102: option ROM 104, 208: latch
    106, 206: Program ROM 202: Option Address Generator
    204: multiplexer OR: option lead signal
    DOP: Option Data
    The preferred embodiment of the present invention thus made will be described with reference to FIG. 2 as follows. 2 is a view showing an option control circuit according to the present invention.
    The option address generator 202 operates by the option read signal OR to generate and output an option address.
    The option address output from the option address generator 202 is input to the multiplexer 204. The multiplexer 204 is also input with an external address delivered via an address bus, and the selection of the output data is made by the option read signal OR.
    The address output from the multiplexer 204 is input to the program ROM 206. The program ROM 206 stores other programs for generating a system control signal together with the option data. The option data is designated with a separate address so as to be distinguished from other programs, and the above-described option address generator 202 generates an address assigned to this option data.
    Data or programs output from the program ROM 206 are transferred to other parts of the system via the data bus. The option data among these is input to the data input terminal D of the latch 208. The latch 208 uses the option read signal OR as a clock.
    Referring to the operation of the present invention made as described above in detail.
    When the reset signal is generated, the option read signal OR is activated to logic value 1 (high level) from this. When the option read signal OR is activated, the option address generator 202 operates to generate an option address. The activated option read signal OR selects and outputs an option address input from the option address generator 202 among two addresses input to the multiplexer 204.
    The option address output from the multiplexer 204 is input to the program ROM 206 so that the option data stored at the address is fetched. The option data fetched from the program ROM 206 is input to the data input terminal D of the latch 208 via the data bus.
    Since the latch 208 uses the option read signal OR as a clock, data is output by the activated option read signal OR, and finally, the option data DOP is output. The option data DOP output from the latch 208 allows to change the setting (option) of the corresponding hardware.
    As described above, it can be seen that the present invention does not include a separate option ROM, and is integrated with a program ROM which is basically built in.
    Accordingly, the present invention provides an effect of suppressing an increase in hardware area and simplifying a design unlike when a separate option ROM is provided by integrating and operating an option ROM and a program ROM.
    权利要求:
    Claims (1)
    [1" claim-type="Currently amended] In the optional control circuit,
    An option address generator 202 which is operated by the option read signal OR to output an option address;
    A multiplexer 204 for inputting an external address and an option address transmitted through an address bus and inputting the option read signal OR as a selection signal;
    A program memory (206) in which a predetermined address is input through the multiplexer (204), and a predetermined system control program including option data is stored;
    And a latch (208) in which data output from the program memory (206) is input through a data bus and the option read signal (OR) is input as a clock signal.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-09-28|Application filed by 김영환, 현대반도체 주식회사
    1998-09-28|Priority to KR1019980040211A
    1998-09-28|Priority claimed from KR1019980040211A
    2000-04-25|Publication of KR20000021213A
    2002-02-19|Application granted
    2002-02-19|Publication of KR100310822B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980040211A|KR100310822B1|1998-09-28|Option control circuit|
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